The memory cells of dynamic random access memories are comprised of two main components: a field-effect transistor and a capacitor. In DRAM cells utilizing a conventional planar capacitor, far more chip surface area is dedicated to the planar capacitor than to the field-effect transistor (FET). Wordlines are generally etched from a polysilicon-1 layer. A doped region of silicon substrate functions as the lower (storage-node) capacitor plate, while a polysilicon-2 generally functions as the upper capacitor plate (cell plate). Although planar capacitors have generally proven adequate for use in DRAM chips up to the one-megabit level, they are considered to be unusable for more advanced DRAM generations. As component density in memory chips has increased, the shrinkage of cell capacitor size has resulted in a number of problems. Firstly, the alpha-particle component of normal background radiation can generate hole-electron pairs in the silicon substrate, which functions as the lower capacitor plate. This phenomena will cause a charge stored within the affected cell capacitor to rapidly dissipate, resulting in a "soft" error. Secondly, the sense-amp differential signal is reduced. This aggravates noise sensitivity and makes it more difficult to design a sense-amp having appropriate signal selectivity. Thirdly, as cell capacitor size is decreased, the cell refresh time must generally be shortened, thus requiring more frequent interruptions for refresh overhead. The difficult goal of a DRAM designer is therefore to increase or, at least, maintain cell capacitance as cell size shrinks, without resorting to processes that reduce product yield or that markedly increase the number of masking and deposition steps in the production process.
All manufacturers of 4-megabit DRAMs are utilizing cell designs based on non-planar capacitors. Two basic non-planar capacitor designs are currently in use: the trench capacitor, and the stacked capacitor. Both types of non-planar capacitors typically require a considerably greater number of masking, deposition and etching steps for their manufacture than does a planar capacitor.
In a trench capacitor, charge is stored primarily vertically, as opposed to horizontally in a planar capacitor. Since trench capacitors are fabricated in trenches which are etched in the substrate, the typical trench capacitor, like the planar capacitor, is subject to soft errors. In addition, there are several other problems inherent in the trench design. One problem is that of trench-to-trench charge leakage, caused by the parasitic transistor effect between adjacent trenches. Another problem is the difficulty of completely cleaning the trenches during the fabrication process; failure to completely clean a trench will generally result in a defective cell.
The stacked capacitor design, on the other hand, has proven somewhat more reliable and easier to fabricate than the trench design. Since both the lower and the upper plates of a typical stacked capacitor are formed from individual polysilicon layers, the stacked capacitor is generally much less susceptible to soft errors than either the planar or trench capacitors. By placing both the wordline and the digitline beneath the capacitive layers, and having the lower layer make contact with the substrate by means of a buried contact, some manufacturers have created stacked capacitor designs in which vertical portions of the capacitor contribute significantly to the total charge storing capacity. Since a stacked capacitor generally covers not only the entire area of a cell (including the cell's access FET), but adjacent field oxide regions as well, capacitance is considerably enhanced over that available from a planar type cell.
There are at least four, performance-degrading design problems associated with the fabrication of stacked-cell DRAM memories that may be ameliorated by implementing the new DRAM manufacturing process disclosed herein. The first is that of excessive bit line resistance which results in low-speed devices. The second problem is that of excessive bit line capacitance that leads to a reduced bit line sense amp signal. The third problem is that of greater-than-optimum cell width due to the need to provide sufficient overlap between bit line mask and bit line contact mask to prevent unwanted substrate trenching within mask alignment tolerances. The fourth problem is that of spacer build-up in storage-node buried contact regions, brought about by the need to insulate not only the upper surfaces, but also the edges of bit lines.
Excessive bit line resistance arises in a conventional stacked cell DRAM memory as the result of the vertical topography. Typically, buried bit lines are formed from conformal polysilicon layers deposited via chemical vapor deposition (CVD). The layers are then silicided and patterned. Since the silicide layer, which carries the majority of the bitline current follows the topography (i.e. by ascending and descending extant word lines), resistance of such non-planar bit lines is increased (compared to those of the planar variety) due to both the poor quality of silicidation on vertical bit line segments and the added length thereof created by the non-planarity.
Excessive bit line capacitance is arises from the proximity of a bit line to the various word lines it traverses. Capacitance is added by the proximity of vertical bit line segments to word line edges. This capacitive component can be largely eliminated with planar bit lines.
Greater-than-optimum cell width, attributable to the necessity of providing sufficient overlap between bit line mask and bit line contact mask to prevent unwanted substrate trenching within mask alignment tolerances, could be eliminated if it were not necessary to etch certain portions of the bitline layer down to the substrate level.
Spacer build-up in storage-node buried contact regions of a stacked-cell DRAM memory is a result of the need to make contact with the substrate between certain word line pairs for both bit line and storage node plate contact. Although the use of a buried, silicided polysilicon bit line reduces step coverage problems that would be associated with the deep bit line vias that would otherwise be required for surface-deposited metal bit lines in a stacked-cell DRAM memory, buried bit lines are typically adjacent the capacitor plates of the finished cell. Hence, it is essential that the top and sides of each bitline be coated with an insulative material. Generally, the bit line process flow follows a sequence of depositing a bit line poly layer, siliciding the bit line poly layer, depositing a first oxide layer on top of the silicided poly layer, then patterning the resulting sandwich to form the bit lines. A second oxide layer is then blanket deposited and anisotropically etched to create spacers on the sides of the bit lines. Unfortunately, the oxide layer used to form the spacers on the sides of the bit lines fills the space between word lines where storage node plate contact is made to a substrate junction. For conventional process flows, the need for bit line side spacers mandates the spacing between the word lines pairs, where storage node plate contact is made, be sufficiently wide to accommodate this superfluous buildup of oxide spacer material.
By planarizing the polysilicon layer from which it patterns bit lines prior to silicidation, Hitachi Corporation has achieved low-resistance bit-line wiring for its 64 megabit DRAMs. The process is explained in a paper presented at the 1990 Symposium on VLSI Technology sponsored by the IEEE entitled "A 1.28 .mu.m.sup.2 Bit-Line Shielded Memory Cell Technology for 64MB DRAMs". The Hitachi process comprises the steps of depositing a thick polysilicon-2 layer through CVD, the poly-2 layer then being planarized in an etch-back step, silicided for resistance reduction, and finally patterned as bit lines. This Hitachi process, however, does not address the problems of excessive bit line capacitance, greater-than-optimum cell width, and spacer build-up in storage-node buried contact regions.
What is needed is a DRAM process flow that will ameliorate all four of the aforementioned problems with a minimum of additional processing steps.